The present invention relates to BiCMOS integrated circuit devices and, in particular, to high-speed BiCMOS logic circuits useful in integrated circuits.
BiCMOS integrated circuits are semiconductor devices in which bipolar technology is combined with complementary metal oxide semiconductor (CMOS) technology. In such an BiCMOS integrated circuit, the higher speed bipolar transistors or transistor circuits are located at the suitable locations in the semiconductor device to use the speed and drive capabilities inherent in bipolar transistors. The CMOS circuits are typically used wherever higher packing densities and lower power consumption of CMOS circuits are suitable, though a bipolar transistor may occupy less area for the same effective current drive.
Typically for any logic circuit, the gate delay is a desired operational parameter characterized by the time at which a logic circuit switches from one logic state to a second state and from the second state to the first. On the other hand, a typical result of high switching speeds is increased power consumption by the logic circuit, which is not desireable. With BiCMOS circuits, though, less power is consumed than with other types of circuits for the same fanout performance.
In most applications of logic circuits, the circuit is required to switch at high speeds in both directions. After a switch from an original logic state to a second logic state, the switch back into the original logic state occurs at the same rate at some later time. In response to these switching requirements, the present invention provides for a BiCMOS logic circuit which is able to switch very quickly, i.e., with small propagation delays, from a first logic state to a second logic state in response to an input signal pulse. The switch back from the second logic state to the first logic state occurs at the same rate but delayed in response to a reset signal pulse timed by a clock signal, or self-timed, from the input signal pulse. In other words, a circuit is used to reset the logic circuit synchronously. Power is saved because a relative high current flows only to switch the logic circuit in the desired direction.